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Peer-reviewed

Multilayer pFIB Trenches for Multiple Tip EBAC/EBIRCH Analysis and Internal Node Transistor Characterization

N S Pronin, Stefano Larentis, Carey Wu, Eric Foote, Gary M. Clark, Khiem Ly, Jacob Levenson, Kristofor Dickson, Charles Petri, Nelson Gomez, Tony Chrastecky

Proceedings - International Symposium for Testing and Failure Analysis · 2023

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Summary

Abstract In this work, we present three case studies that highlight the novelty and effectiveness of using multiple plasma FIB trenches to simultaneously access multiple metal layers for nanoprobing failure analysis. Multilayer access enabled otherwise impossible two-tip current imaging techniques and allowed us to fully characterize suspect logic gate transistors by exposing internal nodes, while preserving higher metal inputs and outputs. The presented case studies focus on late node planar and established FinFET technologies. The delayering techniques used are not necessarily technology dependent, but highly scaled and advanced processes generally require smaller trench areas for multilayer access. The minimum trench dimensions are limited by ion beam imaging resolution and trench-nanop

Source type
Peer-reviewed study
DOI
10.31399/asm.cp.istfa2023p0403
Catalogue ID
BFmoicpf59-4c29od
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